Receiver and its adjustment system and method

ABSTRACT

A receiver and its adjustment system and method that can reduce the effort and the cost required to give good characteristics. The receiver comprises a quadrature detector whose characteristics value is varied by adjusting the capacitance. The quadrature detector comprises a variable capacitance circuit  182  formed on a semiconductor substrate and an LC parallel resonance circuit  20  comprising an inductor  120  and a capacitor  122  formed outside the semiconductor substrate. The characteristic value of the quadrature detector is adjusted by varying the capacitance of the variable capacitance circuit  182.

TECHNICAL FIELD

The present invention relates to a receiver for performing fineadjustment of a quadrature detector and so on and its adjustment systemand method.

BACKGROUND ART

Conventionally, various detection methods are used for an FM receiver,such as a Foster-Seeley detector, a ratio detector and a quadraturedetector. Of these detectors, the quadrature detector eliminates apredetermined high-frequency component from a result of multiplying anintermediate frequency signal of a predetermined frequency by a signalhaving shifted a phase of this signal by π/2 so as to perform FMdetection. It requires a π/2 phase shifter for shifting a phase of aninputted intermediate frequency signal just by π/2. The π/2 phaseshifter is configured by, for instance, combining inductors and coils inparallel or in series.

As there are variations on manufacturing as to the inductors andcapacitors included in the above-mentioned π/2 phase shifter, theirelement constants are also uneven in a certain range. For instance,inductance of the inductors and capacitance of the capacitors are unevenin the range of ±10 percent. As a matter of course, in the case wherethe π/2 phase shifter is configured by combining these inductors andcapacitors, a frequency of which phase shift amount is π/2 gets deviatedfrom the predetermined frequency so that the quadrature detector, thatis, the FM receiver using the quadrature detector cannot obtain goodcharacteristics. For this reason, it conventionally takes the effort andcost to obtain the good characteristics since parts having desiredcharacteristics are selected and used out of significantly variableparts and expensive parts such as ceramic filters are used to stabilizethe frequency.

DISCLOSURE OF THE INVENTION

The present invention has been made in view of such points, and anobject thereof is to provide a receiver capable of reducing such effortand cost to obtain the good characteristics and its adjustment systemand method.

To solve the above-mentioned problems, the receiver of the presentinvention comprises a detector of which characteristic values are variedby adjusting a capacitance value. This detector comprises a variablecapacitance circuit formed on a semiconductor substrate and a resonancecircuit composed of an inductor and a first capacitor formed outside thesemiconductor substrate, where the characteristic values of the detectorare adjustable by varying the capacitance value of the variablecapacitance circuit. Thus, it is possible, even in the case where thereare variations on manufacturing as to element constants of the inductorand capacitor of the resonance circuit comprising the detector, to varythe capacitance value of the variable capacitance circuit formed on thesemiconductor substrate and thereby adjust the characteristic values ofthe detector. Therefore, it is unnecessary, for the sake of obtaininggood characteristics as the detector or the receiver, to select lessvariable parts or use expensive parts so as to reduce the effort andcost.

The above-mentioned variable capacitance circuit should desirablycomprise a plurality of second capacitors and switches for having eachof the second capacitors combined and connected in parallel. Thus, it ispossible, by connecting the second capacitors in parallel while varyingtheir combinations, to obtain large capacitance by using a small numberof the second capacitors.

The plurality of second capacitors should desirably have mutuallydifferent capacitance values, respectively. It is thereby possible toobtain still larger capacitance by varying the combinations of thesecond capacitors.

It is also desirable that each of the above-mentioned plurality ofsecond capacitors be set at twice the capacitance in geometricprogression. It is thereby possible, by combining the second capacitors,to obtain the capacitance values increasing and decreasing atpredetermined intervals.

It is also desirable that the above-mentioned variable capacitancecircuit further comprise a storage unit for storing data of the numberof bits at least more than the number of switches and have a connectionstate of the switches set according to the values of the bits of thedata stored in the storage unit. It is thereby possible to set theconnection state of each switch just by storing predetermined data inthe storage unit so as to reduce the effort on adjusting thecharacteristics of the detector.

It is also desirable that the FM receiver further comprise a nonvolatilememory holding the data corresponding to characteristic values of thedetector for optimizing a receiving state measured in advance and acontrol unit for reading the data held in the memory and storing it inthe storage unit before starting a receiving operation. It is therebypossible to perform adjustment work for each receiver just by acquiringin advance and storing the data for optimizing the receiving state inthe memory so as to reduce the effort on adjusting the receiver to anoptimal receiving state.

It is also desirable that the above-mentioned control unit detectstemperature of the detector and varies the contents of the data storedin the storage unit according to a variance of the temperature beforestarting the receiving operation. It is thereby possible to keep theoptimal receiving state of the receiver even in the case where thetemperature fluctuates and the characteristics of the detector vary.

It is also desirable that the above-mentioned control unit detects apower supply voltage and varies the contents of the data stored in thestorage unit before starting the receiving operation according to avariance of the power supply voltage. It is thereby possible to keep theoptimal receiving state of the receiver even in the case where the powersupply voltage fluctuates and the characteristics of the detector vary.

It is also desirable that the above-mentioned detector be a quadraturedetector having a π/2 phase shifter comprised of the resonance circuitand variable capacitance circuit, where the capacitance value of thevariable capacitance circuit is variable and a phase shift amount of theπ/2 phase shifter against an input signal is thereby accuratelyadjustable to π/2. Even in the case where the element constants of theresonance circuit and other elements are not fixed due to the variationson manufacturing, it is possible, by rendering the capacitance value ofthe variable capacitance circuit variable, to set the phase shift amountof the π/2 phase shifter accurately to π/2 against the input signal.Therefore, it is possible to use various parts of which elementconstants are uneven as-is on manufacturing so that there is no need touse expensive parts. Thus, it is possible to significantly reduce costof parts.

It is also desirable that the above-mentioned semiconductor substratehas other component circuits formed thereon integrally with the variablecapacitance circuit. It is thereby possible to reduce the cost bydecreasing the number of parts.

It is also desirable that the circuits on the above-mentioned substrateare formed by using a CMOS process or a MOS process. It is therebypossible to simplify a manufacturing process and miniaturize the parts.

The adjustment system of the receiver of the present invention adjuststhe above-mentioned receiver to an optimal receiving state, andcomprises a signal generator for inputting a test signal to thereceiver, a measuring instrument for measuring the receiving state ofthe receiver, and an adjusting apparatus for determining the receivingstate of the receiver based on a measurement result by the measuringinstrument and switching the connection state of the plurality of secondcapacitors included in the variable capacitance circuit so as tooptimize the receiving state. An adjustment method of the receiver ofthe present invention is the method of optimizing the receiving state ofthe above-mentioned receiver, and comprises steps of inputting the testsignal to the receiver, measuring the receiving state of the receiver,and determining the receiving state of the receiver based on themeasurement result of the receiving state of the receiver and switchingthe connection state of the plurality of second capacitors included inthe variable capacitance circuit so as to optimize the receiving state.It is possible, by using this adjustment system or performing thisadjustment method, to set an optimal receiving state of the receiverwhile switching the connection state of the plurality of secondcapacitors in the variable capacitance circuit even in the case of usingthe parts of which element constants on manufacturing are significantlyvariable. Thus, it is possible to reduce the effort required forselection of the parts and also reduce the cost of parts.

The adjustment system of the receiver of the present invention adjuststhe receiver having the above-mentioned memory to the optimal receivingstate, and comprises a signal generator for inputting a test signal tothe receiver, a measuring instrument for measuring the receiving stateof the receiver, and a controlling apparatus for determining thereceiving state of the receiver based on the measurement result of themeasuring instrument and determining the data to be stored in thestorage unit and writing the data to the memory so as to optimize thereceiving state.

The adjustment method of the receiver of the present invention is themethod of adjusting the receiver having the above-mentioned memory tothe optimal receiving state, and comprises the steps of inputting a testsignal to the receiver, measuring the receiving state of the receiver,and determining the receiving state of the receiver based on themeasurement result of the receiving state of the receiver, determiningthe data to be stored in the storage unit and writing the data to thememory so as to optimize the receiving state.

Even in the case of using the parts of which element constants onmanufacturing are significantly variable, it is possible, by using thisadjustment system or performing this adjustment method, to keep theoptimal receiving state of the receiver on normal operation just bysetting the optimal receiving state of the receiver while switching theconnection state of the plurality of second capacitors in the variablecapacitance circuit and storing the data of this time in the memory soas to reduce the effort required for selection of the parts and alsoreduce the cost of parts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of an FM receiver accordingto an embodiment;

FIG. 2 is a diagram showing a detailed configuration of a quadraturedetector comprised of an FM detector circuit and an LC parallelresonance circuit;

FIG. 3 is a diagram showing a detailed configuration of a variablecapacitance circuit;

FIG. 4 is a diagram showing an overall configuration of an adjustmentsystem including the FM receiver;

FIG. 5 is a diagram showing a relation between an output Vo of a levelmeter and data N to be stored in a register in the variable capacitancecircuit;

FIG. 6 is a flowchart showing an operating procedure for measuring anoptimal value with a personal computer;

FIG. 7 is a flowchart showing the operating procedure for starting theFM receiver after finishing an adjustment shown in FIG. 6;

FIG. 8 is a flowchart showing the operating procedure of the FM receiverin consideration of temperature variation; and

FIG. 9 is a flowchart showing the operating procedure of the FM receiverin consideration of fluctuation of power supply voltage.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereunder, an FM receiver according to an embodiment of the presentinvention will be described in detail by referring to the drawings.

FIG. 1 is a diagram showing a configuration of the FM receiver accordingto this embodiment. The FM receiver shown in FIG. 1 comprises ahigh-frequency amplifier circuit 11, a mixer circuit 12, a localoscillator 13, intermediate frequency filters 14, 16, an intermediatefrequency amplifier circuit 15, a limit circuit 17, an FM detectorcircuit 18 which are formed as a one-chip part 10, and a stereodemodulator circuit 19, an LC parallel resonance circuit 20, amicrocomputer 21 and an EEPROM 22 provided separately from the one-chippart 10.

An FM modulated wave received by an antenna 9 is amplified by thehigh-frequency amplifier circuit 11, and then a local oscillation signaloutputted from the local oscillator 13 is mixed therewith so as toperform conversion from a high-frequency signal to an intermediatefrequency signal. The intermediate frequency filters 14, 16 are providedin a preceding stage and a subsequent stage to the intermediatefrequency amplifier circuit 15, and extract only predetermined bandcomponents from the intermediate frequency signals that are inputted.The intermediate frequency amplifier circuit 15 amplifies some of theintermediate frequency signals passing through the intermediatefrequency filters 14, 16. The limit circuit 17 amplifies the inputtedintermediate frequency signals at a high gain, and outputs signals offixed amplitude. The FM detector circuit 18 forms a quadrature detectortogether with the LC parallel resonance circuit 20 connected to theoutside of the one-chip part 10, and performs an FM detection process tothe signals of a fixed amplitude outputted from the limit circuit 17.The above-mentioned one-chip part 10 is integrally formed on asemiconductor substrate by using the CMOS process or the MOS process. Asfor this semiconductor substrate, there may be the cases where variousanalog and digital circuits are formed thereon apart from the caseswhere only the circuits configuring the one-chip part 10 shown in FIG. 1are formed thereon. The stereo demodulator circuit 19 performs a stereodemodulation process to FM-detected composite signals outputted from theFM detector circuit 18 so as to generate L signals and R signals.

As for the quadrature detector according to this embodiment comprised ofthe FM detector circuit 18 and LC parallel resonance circuit 20, it isnecessary to generate a signal of which phase is shifted exactly by π/2from the intermediate frequency signal of a predetermined frequency(10.7 MHz for instance) inputted from the limit circuit 17. The LCparallel resonance circuit 20 is used for this reason. However,variations on manufacturing are allowed to an extent as to elementconstants of an inductor 120 and a capacitor 122 configuring the LCparallel resonance circuit 20 and the element constant of the capacitorincluded in the FM detector circuit 18. Therefore, it is almostdifficult to shift the phase of an input signal exactly by 90 degreeswith no adjustment on combining these parts. For this reason, accordingto this embodiment, a variable capacitance circuit (described later) ofwhich capacitance value is variable is included in the FM detectorcircuit 18. And it is possible, by adjusting the capacitance value ofthis circuit, to shift the phase of the input signal exactly by π/2.

The microcomputer 21 is a control unit for, on starting up the FMreceiver, setting the capacitance value of the variable capacitancecircuit included in the FM detector circuit 18 to a predeterminedadjusted value. As for this adjusted value, a value measured in advanceon manufacturing the FM receiver is used. The EEPROM 22 is a nonvolatilememory for storing this adjusted value.

Next, the quadrature detector of this embodiment will be described indetail. FIG. 2 is a diagram showing a detailed configuration of thequadrature detector comprised of the FM detector circuit 18 and the LCparallel resonance circuit 20.

As shown in FIG. 2, the FM detector circuit 18 comprises a capacitor180, a variable capacitance circuit 182, a multiplier 184 and an LPF(low-pass filter) 186. A π/2 phase shifter 190 is comprised of thecapacitor 180 and variable capacitance circuit 182 and also the LCparallel resonance circuit 20 connected to the outside. The variablecapacitance circuit 182 is connected to the LC parallel resonancecircuit 20 in parallel, and the capacitor 180 is further connected inseries to these parallel circuits. The capacitance value of the variablecapacitance circuit 182 is arbitrarily settable in a predeterminedrange. And the capacitance value is adjusted to set a phase shift amountof the π/2 phase shifter 190 to exactly π/2 against the intermediatefrequency signal of the predetermined frequency.

The multiplier 184 multiplies the intermediate frequency signaloutputted from the limit circuit 17 by the signal having the phase ofthe intermediate frequency signal shifted by π/2 with the π/2 phaseshifter 190. The LPF 186 eliminates unnecessary high-frequencycomponents included in an output signal of the multiplier 184.

FIG. 3 is a diagram showing a detailed configuration of the variablecapacitance circuit 182. As shown in FIG. 3, the variable capacitancecircuit 182 comprises a register 188, switches Sw0 to Sw7 and capacitorsC0 to C7. The register 188 is the storage unit for storing 8-bit data,and outputs the bits from its lowest order d0 to its highest order bitd7 in parallel.

The capacitor C0 has its one end connected to one end of the LC parallelresonance circuit 20 and its other end grounded via the switch Sw0. Asthe other end of the LC parallel resonance circuit 20 is grounded sothat, on turning the switch Sw0 on, the capacitor C0 is furtherconnected to the LC parallel resonance circuit 20 in parallel. Likewise,each of the capacitors C1 to C7 has its one end connected to one end ofthe LC parallel resonance circuit 20 and its other end grounded via oneof the switches Sw1 to Sw7. If each of the switches Sw1 to Sw7 is turnedon, one of the capacitors C1 to C7 corresponding thereto is connected tothe LC parallel resonance circuit 20 in parallel.

Each of the switches Sw0 to Sw7 has its on and off state setcorrespondingly to the values of the bits d0 to d7 of the 8-bit datastored in the register 188. To be more precise, the switch Sw0 iscorresponding to the lowest order bit do so that it is turned on whenthe value of do is “1” and turned off when “0.” Likewise, each of theswitches Sw1 to Sw7 is corresponding to each of the first bit d1 to thehighest order bit d7 so that it is turned on when the value of each bitis “1” and turned off when “0.”

When the capacitance of the capacitor C0 is Ct (=2⁰×Ct), the capacitanceof the capacitor C1 is set as 2Ct (=2¹×Ct), that of the capacitor C2 as4Ct (=2²×Ct) . . . , and that of the capacitor C7 as 128 Ct (=2⁷×Ct)respectively.

The above-mentioned variable capacitance circuit 182 has the lowestcapacitance Cmin (=Ct) when only the switch Sw0 connected in series tothe capacitor C0 is turned on, and has the highest capacitance Cmax(=(2⁰+2¹+2²+2³+2⁴+2⁵+2⁶+2⁷)Ct) when the switches Sw0 to Sw7 connected toall the capacitors C0 to C7 respectively are turned on. It is possibleto vary the contents of the data stored in the register 188 andappropriately turn on and off the switches Sw0 to Sw7 so as to switchthe capacitance value of the entire variable capacitance circuit 182stepwise in units of Ct in the range of Cmin to Cmax.

Thus, even in the case where there are variations in the elementconstants of the inductor 120 and capacitor 122 configuring the LCparallel resonance circuit 20 and the element constants of the capacitor180 included in the FM detector circuit 18 so that the phase shiftamount of the π/2 phase shifter 190 configured by combining the LCparallel resonance circuit 20, capacitor 180 and so on is not exactlyπ/2 against the intermediate frequency signal of 10.7 MHz for instance,it is possible to securely set it to π/2 by setting the capacitancevalue of the variable capacitance circuit 182 at an adequate value.

It is empirically known that there are variations in the range of ±5percent as to the element constants of the inductor 120 and capacitor122 configuring the LC parallel resonance circuit 20. To be morespecific, there are variations in the range of ±10 percent as to theentire LC parallel resonance circuit 20. Therefore, it is sufficient ifa resonance frequency is variable in the range of ±10 percent (2140 kHz)in proximity to the intermediate frequency signal of 10.7 MHz. It isalso known that it is sufficient if the resonance frequency is variablein units of 10 kHz in the above frequency range, where the number ofnecessary steps M is 214 (=2140/10). If the data to be stored in theabove-mentioned register 188 is 8 bits, a practical adjustment becomespossible by securing 256(=2⁸) as the number of steps.

Next, a concrete adjustment method of the FM receiver of this embodimentwill be described. FIG. 4 is a diagram showing an overall configurationof the adjustment system including the FM receiver. This adjustmentsystem comprises a signal generator (SG) 200, a level meter 202 and a PC(personal computer) 210 in addition to an FM receiver 1 of thisembodiment.

The signal generator 200 generates a test signal of a predeterminedfrequency. For instance, the test signal of a frequency included in areceiving band of an FM broadcast is outputted from the signal generator200 to be inputted to the high-frequency amplifier circuit 11. The levelmeter 202 is a measuring instrument for measuring the level of thesignal outputted from the FM detector circuit 18 included in the FMreceiver. According to this embodiment, an output signal of the FMdetector circuit 18 is inputted to the level meter 202. However, it isalso possible to input the output signal of the stereo demodulatorcircuit 19 to the level meter 202.

The PC 210 operates as a controlling apparatus which executes apredetermined program for adjustment stored in a memory and a hard diskdrive and thereby adjusts the capacitance value of the variablecapacitance circuit 182 in the FM detector circuit 18 while monitoringthe output of the level meter 202 so as to write the result thereof tothe EEPROM 22.

FIG. 5 is a diagram showing a relation between an output Vo of the levelmeter 202 and data N to be stored in the register 188 in the variablecapacitance circuit 182. As for the data N to be stored in the register188, there exists an optimal value N1 at which the output Vo of thelevel meter 202 becomes maximum when the phase shift amount of the π/2phase shifter 190 including the variable capacitance circuit 182 is π/2.The optimal value N1 is different as to each FM receiver according tovariations on manufacturing the inductor 120 and capacitor 122, andsoon, configuring the LC parallel resonance circuit 20. The PC 210measures the optimal value N1 as to each FM receiver.

FIG. 6 is a flowchart showing an operating procedure for measuring theoptimal value N1 with the PC 210. First, the PC 210 sets an initialvalue N0 as the data N to be stored in the register 188 (step 100). Forinstance, an average value of a plurality of the optimal values N1corresponding to a plurality of the FM receivers 1 obtained by themeasurements so far is used as the initial value N0. After the initialvalue N0 is stored in the register 188, the PC 210 fetches the output Voof the level meter 202 (step 101).

After updating the data N (=N0) to be stored in the register 188 byadding 1 thereto (step 102), the PC 210 fetches an output Vo′ of thelevel meter 202 (step 103).

Next, the PC 210 determines whether or not the output Vo′ of the levelmeter 202 fetched for the second time approximately matches with theoutput Vo of the level meter 202 fetched for the first time (step 104).As shown in FIG. 5, the output Vo of the level meter 202 varies littleonce the data N to be stored in the register 188 is included in a rangeA in proximity to the optimal value N1. In the step 104, it isdetermined whether or not the data N is included in the range A. In thecase where the outputs Vo and Vo′ of the level meter 202 fetched twiceare approximately equal (including both the cases where they matchcompletely and where they do not match completely but their differenceis within a predetermined value), an affirmative judgment is made indetermination in the step 104. Next, the PC 210 writes the data N to theEEPROM 22 (step 105), and finishes a series of adjustment operations.

In the case where the outputs Vo and Vo′ of the level meter 202 fetchedtwice do not match, a negative judgment is made indetermination in thestep 104, and the PC 210 determines next whether or not the output Vo′of the level meter 202 fetched later is larger than the output Vofetched earlier (step 106). The case where the output Vo′ fetched lateris larger than the output Vo fetched earlier is the case where the dataN at the time is included in a range B shown in FIG. 5. In this case, anaffirmative judgment is made in the step 106. Next, the PC 210 updatesthe value of the data N by adding 1 (step 107), and then returns to thestep 103 so as to repeat a fetch operation of the output Vo′ of thelevel meter 202. Inversely, in the case where the output Vo′ fetchedlater is smaller than the output Vo fetched earlier and the data N atthe time is included in a range C shown in FIG. 5, a negative judgmentis made in determination in the step 106. Next, the PC 210 updates thevalue of the data N by subtracting 1 (step 108), and then returns to thestep 103 so as to repeat the fetch operation of the output Vo′ of thelevel meter 202.

Thus, according to the FM receiver 1 of this embodiment, it is possibleto vary the capacitance value of the variable capacitance circuit 182 byrendering the data N to be stored in the register 188 variable so as toaccurately adjust the frequency at which the phase shift amount is π/2on the π/2 phase shifter 190 configured by the variable capacitancecircuit 182, capacitor 180 and LC parallel resonance circuit 20. Inparticular, it is possible to set the capacitance values of theplurality of capacitors C0 to C7 included in the variable capacitancecircuit 182 to be twice in sequence and use them by connecting them inparallel in adequate combinations so as to vary the capacitance valuesat fixed intervals by combining a small number of capacitors.

FIG. 7 is a flowchart showing the operating procedure for starting theFM receiver 1 after finishing the adjustment shown in FIG. 6.

On having a power switch (not shown) of the FM receiver 1 turned on, themicrocomputer 21 reads the data N stored in the EEPROM 22 (step 200),and sets it in the register 188 in the variable capacitance circuit 182(step 201). As the data N has the optimal value N1 set up therein, whichis measured in advance to operate the FM detector circuit 18 in anoptimal state, it is possible to set the data N in the register 188 soas to set an optimal receiving state each time the power switch of theFM receiver 1 is turned on. Thus, the FM receiver 1 starts normalreceiving operation after the data N is completely set (step 202).

Thus, according to the receiver of this embodiment, even in the casewhere there are variations in the element constants of the inductor 120and capacitor 122 included in the LC parallel resonance circuit 20configuring the quadrature detector, it is possible to vary thecapacitance value of the variable capacitance circuit 182 formed on thesemiconductor substrate and thereby adjust characteristic values of thedetector. Therefore, it is not necessary to select less variable partsor use expensive parts in order to obtain good characteristics as thedetector or receiver, and so the effort and cost can be alleviated.

As for the variable capacitance circuit 182, it is possible to connectthe capacitors C0 to C7 in parallel while varying their combinations soas to obtain large capacitance by using a small number of thecapacitors. It is also possible to have different capacitance values forthese capacitors so as to obtain still larger capacitance by varying thecombinations of the capacitors connected in parallel. In particular, itis possible, by setting the capacitance values of the capacitors to havetwice the capacitance mutually and varying the combinations of thecapacitors, to obtain the capacitance values increasing and decreasingat predetermined intervals.

The variable capacitance circuit 182 comprises the register 188 forstoring the data of the number of bits corresponding to the number ofthe switches Sw0 to Sw7. It is possible to set the connection state ofeach switch just by storing the data in the register 188 so as toalleviate the effort on adjusting the characteristics of the detector.

The receiver also comprises the EEPROM 22 for, on having thecharacteristic values of the detector for implementing the optimalreceiving state measured in advance, holding the data corresponding tothe characteristic values, and the microcomputer 21 for reading the dataheld by the EEPROM 22 and storing it in the register 188 before startingthe receiving operation. Therefore, it is possible to perform adjustmentwork for each receiver just by acquiring in advance the data foroptimizing the receiving state and storing it in the EEPROM 22 so as toalleviate the effort on adjusting the receiver to the optimal receivingstate.

As the semiconductor substrate has other component circuits integrallyformed with the variable capacitance circuit 182 thereon, it is possibleto reduce the cost by decreasing the number of parts. In particular, itis possible to form the circuits on the semiconductor substrate by usingthe CMOS process or MOS process so as to simplify the manufacturingprocess and miniaturize the parts.

The present invention is not limited to the above embodiment, andvarious modifications thereof are possible within the gist of thepresent invention. According to the above embodiment, the data N forimplementing the optimal receiving state of the FM receiver is measuredin advance and stored in the EEPROM 22 to read the data N on turning onthe power switch. In the case where temperature variation is intense orin the case of using an element of which characteristic values varysignificantly according to the temperature variation, however, it isdesirable to reset the data N not only on turning on the power switchbut also on significant temperature variation.

FIG. 8 is a flowchart showing the operating procedure of the FM receiverin consideration of the temperature variation. As with the FM receivernot considering the temperature variation, on turning on the powerswitch (not shown), the microcomputer 21 first reads the data N held bythe EEPROM 22 (step 200), and sets it in the register 188 in thevariable capacitance circuit 182 (step 201). Thereafter, the FM receiverstarts the normal receiving operation (step 202).

Next, the microcomputer 21 measures ambient temperature of the LCparallel resonance circuit 20 and the FM detector circuit 18 (step 203).This measurement is performed by using an element of which current valueand both end voltage are dependent on the temperature. For instance, theabove-mentioned ambient temperature can be easily measured by passing acurrent through a diode and checking that value.

Next, the microcomputer 21 determines whether or not there has beenpredetermined temperature variation (step 204). It is determined whetheror not there has been the temperature variation exceeding apredetermined range (±10 degrees or more, for instance) in reference tothe temperature at the time of setting the data N in the register 188.In the case where there has been little temperature variation ortemperature variation with little variance, a negative judgment is madein the determination in the step 204 and this determination operation isrepeated.

In the case where there has been temperature variation exceeding thepredetermined range, an affirmative judgment is made in thedetermination in the step 204, and then the microcomputer 21 varies thecontents of the data N stored in the register 188 to a valuecorresponding to the temperature after the variation (step 205). It ispossible to measure in advance or acquire the extent to which the data Nstored in the register 188 should be varied according to the extent ofthe temperature variation by calculating it based on temperaturecoefficients such as the inductance of the inductor 120 and thecapacitance of capacitor 122. Once the value of the data N stored in theregister 188 is varied, it returns to the step 203 so as to repeat theprocess from temperature measurement onward.

Thus, even in the case where the temperature varies and thecharacteristics of the quadrature detector thereby vary, it is possibleto adjust the capacitance value of the variable capacitance circuit 182according to the varying temperature so as to constantly implement theoptimal receiving state.

It is also feasible to monitor fluctuation of the power supply voltageafter the FM receiver starts the receiving operation and appropriatelyvary the value of the data N to be stored in the register 188.

FIG. 9 is a flowchart showing the operating procedure of the FM receiverin consideration of the fluctuation of the power supply voltage. As withthe FM receiver not considering the temperature variation, on turning onthe power switch (not shown), the microcomputer 21 first reads the dataN held by the EEPROM 22 (step 200), and sets it in the register 188 inthe variable capacitance circuit 182 (step 201). Thereafter, the FMreceiver starts the normal receiving operation (step 202).

Next, the microcomputer 21 measures the power supply voltage (step 210).For instance, this measurement can be performed by using an A/D(analog-digital) converter to directly detect a voltage of a powersupply terminal or comparing a predetermined reference voltage to thevoltage of the power supply terminal with a voltage comparator.

Next, the microcomputer 21 determines whether or not there has beenpredetermined power supply voltage variation (step 211). It isdetermined whether or not there has been power supply voltage variationexceeding a predetermined range (±0.3 V or more, for instance) inreference to the power supply voltage at the time of setting the data Nin the register 188 (in the case where, immediately after starting theoperation, the data N has never been updated, it is determined inreference to the power supply voltage at the time of setting the data Nbefore shipment). In the case where there has been little power supplyvoltage variation or power supply voltage variation with littlevariance, a negative judgment is made in the determination in the step211 and this determination operation is repeated.

In the case where there has been power supply voltage variationexceeding the predetermined range, an affirmative judgment is made inthe determination in the step 211, and then the microcomputer 21 variesthe contents of the data N stored in the register 188 to a valuecorresponding to the power supply voltage after the variation (step212). It is possible to measure in advance or acquire by calculationbased on simulation the extent to which the data N stored in theregister 188 should be varied according to the extent of the powersupply voltage variation. Once the value of the data N stored in theregister 188 is varied, it returns to the step 210 so as to repeat theprocess from the power supply voltage measurement onward.

According to the above-mentioned embodiment, the characteristics of thequadrature detector were adjusted. It is also possible, however, toapply the present invention to the detector of another method if thecharacteristic values are variable by adjusting the capacitance value ofthe variable capacitance circuit 182.

According to the above-mentioned embodiment, the receiving state of thereceiver was measured by using the level meter 202. It is also possible,however, to use a distortion meter. In the case of using the distortionmeter, the receiver is in the best receiving state when the distortionmeter is at the lowest output level. Therefore, the subjects of valuecomparison should be reversed in the determination in the step 106 ofFIG. 6 so as to determine whether or not the output (Vo′) of thedistortion meter fetched later is smaller than the output (Vo) fetchedearlier.

INDUSTRIAL APPLICABILITY

According to the present invention, as described above, it is possible,even in the case where there are variations on manufacturing as to theelement constants of the inductor and capacitor of the resonance circuitcomprising the detector, to vary the capacitance value of the variablecapacitance circuit formed on the semiconductor substrate and therebyadjust the characteristic values of the detector. Therefore, it isunnecessary, for the sake of obtaining good characteristics as thedetector or the receiver, to select less variable parts or use expensiveparts so as to alleviate the effort and cost.

1. A receiver comprising a detector of which characteristic values arevaried by adjusting a capacitance value, characterized in that: thedetector comprises a variable capacitance circuit formed on asemiconductor substrate and a resonance circuit composed of an inductorand a first capacitor formed outside the semiconductor substrate; andthe characteristic values of the detector are adjustable by varying thecapacitance value of the variable capacitance circuit.
 2. The receiveraccording to claim 1, characterized in that the variable capacitancecircuit comprises a plurality of second capacitors and switches forhaving each of the second capacitors combined and connected in parallel.3. The receiver according to claim 2, characterized in that each of theplurality of second capacitors has a different capacitance from oneanother.
 4. The receiver according to claim 2, characterized in thateach of the plurality of second capacitors is set at twice thecapacitance mutually.
 5. The receiver according to claim 2,characterized in that the variable capacitance circuit further comprisesa storage unit for storing data of the number of bits at least more thanthe number of switches and has a connection state of the switches setaccording to the values of the bits of the data stored in the storageunit.
 6. The receiver according to claim 5, characterized by furthercomprising: a nonvolatile memory holding the data corresponding tocharacteristic values of the detector for optimizing a receiving statemeasured in advance; and a control unit for reading the data held in thememory and storing it in the storage unit before starting a receivingoperation.
 7. The receiver according to claim 6, characterized in thatthe control unit detects temperature of the detector and varies thecontents of the data stored in the storage unit according to a varianceof the temperature before starting the receiving operation.
 8. Thereceiver according to claim 6, characterized in that the control unitdetects a power supply voltage and varies the contents of the datastored in the storage unit according to the variance of the power supplyvoltage before starting the receiving operation.
 9. The receiveraccording to claim 1, characterized in that the detector is a quadraturedetector having π/2 phase shifter comprised of the resonance circuit andvariable capacitance circuit; and the capacitance value of the variablecapacitance circuit is variable and a phase shift amount of the π/2phase shifter against an input signal is thereby accurately adjustableto π/2.
 10. The receiver according to claim 1, characterized in that thesemiconductor substrate has other component circuits formed thereonintegrally with the variable capacitance circuit.
 11. The receiveraccording to claim 1, characterized in that the circuits on thesemiconductor substrate are formed by using a CMOS process or a MOSprocess.
 12. An adjustment system for adjusting the receiver accordingto claim 1 to an optimal receiving state, characterized by comprising: asignal generator for inputting a test signal to the receiver; ameasuring instrument for measuring the receiving state of the receiver;and an adjusting apparatus for determining the receiving state of thereceiver based on a measurement result of the measuring instrument andswitching a connection state of the plurality of second capacitorsincluded in the variable capacitance circuit so as to optimize thereceiving state.
 13. An adjustment system for adjusting the receiveraccording to claim 6 to an optimal receiving state, characterized bycomprising: a signal generator for inputting a test signal to thereceiver; a measuring instrument for measuring the receiving state ofthe receiver; and a controlling apparatus for determining the receivingstate of the receiver based on the measurement result of the measuringinstrument and determining the data to be stored in the storage unit andwriting the data to the memory so as to optimize the receiving state.14. An adjustment method for adjusting the receiver according to claim 1to an optimal receiving state, characterized by comprising steps of:inputting a test signal to the receiver; measuring the receiving stateof the receiver; and determining the receiving state of the receiverbased on the measurement result of the receiving state of the receiverand switching a connection state of the plurality of second capacitorsincluded in the variable capacitance circuit so as to optimize thereceiving state.
 15. An adjustment method for adjusting the receiveraccording to claim 6 to an optimal receiving state, characterized bycomprising the steps of: inputting a test signal to the receiver;measuring the receiving state of the receiver; and determining thereceiving state of the receiver based on the measurement result of thereceiving state of the receiver, determining the data to be stored inthe storage unit and writing the data to the memory so as to optimizethe receiving state.